\fI(Geneva, 1972; amended at Geneva, 1976 and 1980,\fR
.sp 9p
.RT
.ce 0
.sp 1P
.ce 1000
\fIMalaga\(hyTorremolinos, 1984 and Melbourne, 1988)\fR
.ce 0
.sp 1P
.sp 2P
.LP
The\ CCITT,
.sp 1P
.RT
.sp 1P
.LP
\fIconsidering\fR
.sp 9p
.RT
.PP
(a)
that Recommendations X.1 and X.2 define the
services and facilities to be provided by a public data network;
.PP
(b)
that Recommendation X.92 defines the hypothetical
reference connections for public synchronous data networks;
.PP
(c)
that Recommendation X.96 defines \fIcall progress\fR \|
signals;
.PP
(d)
that the necessary elements for an interface
Recommendation should be defined in architectural levels;
.PP
(e)
that it is desirable for characteristics of the
interface between the DTE and DCE of a public data network to be
standardized,
.sp 1P
.LP
\fIunanimously recommends\fR
.sp 9p
.RT
.PP
that the interface between the DTE and DCE in
public data
networks
for user classes of service employing
start\(hystop
transmission
should be as defined in this Recommendation.
.sp 2P
.LP
\fB1\fR \fBScope\fR
.sp 1P
.RT
.PP
1.1
This Recommendation defines the physical characteristics and
call control procedures for a general purpose interface between DTE and
DCE for user classes of service, as defined in Recommendation\ X.1, employing
start\(hystop transmission.
.sp 9p
.RT
.PP
1.2
The formats and procedures for \fIselection\fR , \fIcall progress\fR \|and
\fIDCE provided information\fR are included in this Recommendation.
.PP
1.3
The provision for duplex operation is covered.
.sp 2P
.LP
\fB2\fR \fBDTE/DCE physical interface elements\fR
.sp 1P
.RT
.sp 1P
.LP
2.1
\fIInterchange circuits\fR
.sp 9p
.RT
.PP
A list of the interchange circuits concerned is presented in
Table\ 1/X.20. Definitions of these interchange circuits are given in
Recommendation\ X.24.
.bp
.RT
.ce
\fBH.T. [T1.20]\fR
.ce
TABLE\ 1/X.20
.ps 9
.vs 11
.nr VS 11
.nr PS 9
.TS
center box;
cw(48p) | cw(48p) | cw(48p) sw(48p) , ^ | ^ | c | c.
Interchange circuit Interchange circuit name Direction
to DCE from DCE
_
.T&
cw(48p) | lw(48p) | lw(48p) | lw(48p) .
G (see Note) T{
Signal ground or common return
T}
.T&
cw(48p) | lw(48p) | cw(48p) | lw(48p) .
G a DTE common return X
.T&
cw(48p) | lw(48p) | cw(48p) | cw(48p) .
G b DCE common return X
.T&
cw(48p) | lw(48p) | cw(48p) | cw(48p) .
T Transmit X
.T&
cw(48p) | lw(48p) | cw(48p) | cw(48p) .
R Receive X
.TE
.LP
\fINote\fR
\ \(em\ This conductor may be used to reduce environmental signal interference at the interface. In case of shielded interconnecting cable, the additional
connection considerations are part of Recommendations\ X.24 and ISO\ 4903.
.nr PS 9
.RT
.ad r
\fBTable 1/X.20 [T1.20], p.\fR
.sp 1P
.RT
.ad b
.RT
.sp 1P
.LP
2.2
\fIElectrical characteristics\fR
.sp 9p
.RT
.PP
The electrical characteristics of the interchange circuits at the DCE side
of the interface will comply with Recommendation\ X.26.
.PP
The electrical characteristics at the DTE side of the interface may be
applied according to Recommendations\ X.26, X.27 (without cable termination
in the load), or Recommendation\ V.28.
.PP
For interworking between a V.28\(hyDTE and a X.26\(hyDCE refer to
Recommendation X.26 and ISO\ 4903.
.RT
.sp 1P
.LP
2.3
\fIMechanical characteristics\fR
.sp 9p
.RT
.PP
Refer to ISO 4903 (15\(hypole DTE/DCE interface connector and contact number
assignments) for mechanical arrangements.
.RT
.sp 1P
.LP
2.4
\fIFault conditions of interchange circuits\fR
.sp 9p
.RT
.PP
For the association of the receiver circuit\(hyfailure detection
to particular interchange circuits in accordance with the type of failure
detection, see Recommendation\ X.26, \(sc\ 11 and Recommendation\ X.27,
\(sc\ 9.
.RT
.sp 1P
.LP
2.4.1
\fICircuit R in failure state\fR
.sp 9p
.RT
.PP
The DTE should interpret a fault condition on circuit R as r\ =\ 0, using
failure detection type\ 2. When the electrical characteristics are applied
according to Recommendation\ V.28, the DTE should interpret generator in
power\(hyoff condition or open\(hycircuited interconnecting cable as a
binary\ 0.
.RT
.sp 1P
.LP
2.4.2
\fICircuit T in failure state\fR
.sp 9p
.RT
.PP
The DCE will interpret a fault condition on circuit T as t\ =\ 0,
using failure detection type\ 2.
.RT
.sp 2P
.LP
\fB3\fR \fBCall control characters and
\fBerror checking\fR
.sp 1P
.RT
.PP
All characters for call control purposes are selected from
International Alphabet No.\ 5 according to Recommendation\ T.50.
.PP
Even parity according to Recommendation\ X.4 applies for IA5
characters interchanged for call control purposes.
.bp
.RT
.sp 2P
.LP
\fB4\fR \fBElements of the\fR
\fBcall control phase\fR \fBfor\fR
\fBcircuit\fR \fBswitched service\fR
.sp 1P
.RT
.PP
The state diagram provided in Figure A\(hy1/X.20 shows the
relationship between the various \fIcall control\fR phase states as defined
below, together with the recognized transactions between these states under
normal
operating conditions. Illustrated examples of the time sequence relationships
between these states and associated time\(hyout operation are provided
in
Figure\ B\(hy1/X.20.
.PP
The \fIcall control\fR \|phase can be terminated by either the DTE or the
DCE by \fIclearing\fR as defined in \(sc\ 6 below.
.RT
.sp 1P
.LP
4.1
\fIEvents of the call control procedures\fR
.sp 9p
.RT
.PP
(See Figure A\(hy1/X.20.)
.RT
.sp 1P
.LP
4.1.1
\fIReady (state 1)\fR
.sp 9p
.RT
.PP
Circuits T and R show binary 0.
.RT
.sp 1P
.LP
4.1.2
\fICall request (state 2)\fR
.sp 9p
.RT
.PP
The calling DTE shall indicate a request for a call by signalling steady
binary condition t\ =\ 1 provided that it was previously signalling \fIDTE\fR
\fIready\fR (t\ =\ 0).
.RT
.sp 1P
.LP
4.1.3
\fIProceed\(hyto\(hyselect (state 3)\fR
.sp 9p
.RT
.PP
When the network is prepared to receive selection information, the DCE
will signal steady binary con
dition\ r\ =\ 1.
.PP
The \fIproceed\(hyto\(hyselect\fR \|signal will start within 6 seconds of the
\fIcall request\fR being sent.
.RT
.sp 1P
.LP
4.1.4
\fISelection signal sequence (state 4)\fR
.sp 9p
.RT
.PP
The \fIselection\fR \|signal sequence shall be transmitted by the DTE on
circuit\ T.
.PP
The format of \fIselection\fR \|signal sequence is defined in \(sc 4.6.1
below.
.PP
The information content and coding of the \fIselection\fR \|signal sequence
is contained in Annex\ G and Recommendation\ X.121.
.PP
The \fIselection\fR \|signal sequence shall start within 6 seconds of the
\fIproceed\(hyto\(hyselect\fR \| being received and shall be completed
within 36 seconds.
.PP
The maximum permissible interval between individual selection
characters is 6\ seconds.
.RT
.sp 1P
.LP
4.1.5
\fIDTE waiting (state 5)\fR
.sp 9p
.RT
.PP
During \fIDTE waiting\fR \|, the DTE signals steady binary condition
t\ =\ 1.
.RT
.sp 1P
.LP
4.1.6
\fIIncoming call (state 8)\fR
.sp 9p
.RT
.PP
The DCE will indicate an incoming call by signalling steady binary condition
r\ =\ 1.
.RT
.sp 1P
.LP
4.1.7
\fICall accepted (state 9)\fR
.sp 9p
.RT
.PP
The DTE shall accept the incoming call not later than 600\ ms by
signalling the steady state binary condition t\ =\ 1.
.PP
10\(hy100\ ms thereafter, the DTE transmits the call control character
0/6 (ACK).
.RT
.sp 1P
.LP
4.1.8
\fICall not accepted (state 18)\fR
.sp 9p
.RT
.PP
If the DTE does not wish to accept the incoming call it shall
signal this not later than 600\ ms by changing circuit T to steady binary
condition\ 1.
.PP
10\(hy100 ms thereafter, the DTE shall transmit the call control
character\ 1/5 (NAK) followed by \fIDTE clear request\fR (state 13).
\fI(Geneva, 1972; amended at Geneva, 1976 and 1980,\fR
.sp 9p
.RT
.ce 0
.sp 1P
.ce 1000
\fIMalaga\(hyTorremolinos, 1984 and Melbourne, 1988)\fR
.ce 0
.sp 1P
.ce 1000
CONTENTS
.ce 0
.sp 1P
.LP
Preface
.sp 1P
.RT
.sp 2P
.LP
1
Scope
.sp 1P
.RT
.LP
2
DTE/DCE physical interface elements
.LP
3
Alignment of call control characters and error
checking
.LP
4
Elements of the call control phase for circuit switched
service
.LP
5
Data transfer phase
.LP
6
Clearing phase
.LP
7
Test loops
.sp 2P
.LP
\fIAnnex\ A\fR \ \(em
Interface signalling state diagrams
.sp 1P
.RT
.LP
\fIAnnex\ B\fR \ \(em
Interface signalling sequence diagrams and time\(hyout
operation
.LP
\fIAnnex\ C\fR \ \(em
DTE time\(hylimits and DCE time\(hyouts
.LP
\fIAnnex\ D\fR \ \(em
Formats of Selection, Call progress and line identification
signals
.LP
\fIAnnex\ E\fR \ \(em
Interworking between DTEs conforming to
Recommendations\ X.21 and X.21\|\fIbis\fR
.LP
\fIAnnex\ F\fR \ \(em
Coding of Call progress signals
.LP
\fIAnnex\ G\fR \ \(em
Facility request, Indicator and Parameter
coding
.LP
\fIAnnex\ H\fR \ \(em
Information content of DCE\(hyprovided information
.LP
\fIAnnex\ I\fR \ \(em
Cross reference and transition
tables
.bp
.LP
\fBPreface\fR
.sp 1P
.RT
.sp 2P
.LP
The\ CCITT,
.sp 1P
.RT
.sp 1P
.LP
\fIconsidering\fR
.sp 9p
.RT
.PP
(a)
that Recommendations X.1 and X.2 define the
services and facilities to be provided by a public data network;
.PP
(b)
that Recommendation X.92 defines the hypothetical
reference connections for synchronous public data networks;
.PP
(c)
that Recommendation X.96 defines
\fIcall progress\fR \| signals
;
.PP
(d)
that the necessary elements for an interface
Recommendation should be defined in architectural levels;
.PP
(e)
that it is desirable for characteristics of the
interface between the DTE and DCE of a public data network to be
standardized,
.sp 1P
.LP
\fIunanimously declares the view\fR
.sp 9p
.RT
.PP
that the interface between the DTE and DCE in public data networks for
user classes of service employing synchronous transmission should be as
defined in this Recommendation.
.sp 2P
.LP
\fB1\fR \fBScope\fR
.sp 1P
.RT
.PP
1.1
This Recommendation defines the physical characteristics and
call control procedures for a general purpose interface between DTE and
DCE for user classes of service, as defined in Recommendation\ X.1, employing
synchronous transmission.
.sp 9p
.RT
.PP
1.2
The formats and procedures for \fIselection\fR , \fIcall progress\fR \|and
\fIDCE\(hyprovided information\fR \| are included in this Recommendation.
.PP
1.3
The provision for duplex operation is covered.
.PP
1.4
The operation of the interface for half duplex operation when the data
circuit interconnects with Recommendation\ X.21\|\fIbis\fR DTEs is described
in Annex\ E. Half duplex operation between X.21 DTEs is for further study
when such new facilities are identified.
.LP
\fB2\fR \fBDTE/DCE physical interface elements\fR
.sp 1P
.RT
.sp 2P
.LP
2.1
\fIElectrical characteristics\fR
.sp 1P
.RT
.sp 1P
.LP
2.1.1
\fIData signalling rates of 9600 bit/s and below\fR
.sp 9p
.RT
.PP
The electrical characteristics of the interchange circuits at the DCE side
of the interface will comply with Recommendation\ X.27 without cable
termination in the load. The electrical characteristics at the DTE side of
the interface may be applied according to either Recommendation\ X.27 either
with or without cable termination in the load, or Recommendation\ X.26.
The B` leads of receivers in an X.26 DTE must be brought out to the interface
individually and not connected together. (See \(sc\ 2.2 below.)
.PP
\fINote\fR \ \(em\ In certain instances where X.27 circuits are implemented
on both sides of the interface, it may be necessary to add either serial
impedance matching resistors or parallel cable terminating resistors as
specified in
X.27 to assure proper operation of the interchange circuits.
.RT
.sp 1P
.LP
2.1.2
\fIData signalling rates above 9600 bit/s\fR
.sp 9p
.RT
.PP
The electrical characteristics of the interchange circuits at both the
DCE side and the DTE side of the interface will comply with
Recommendation\ X.27 with or without implementation of the cable termination
in the load.
.bp
.RT
.sp 1P
.LP
2.2
\fIMechanical characteristics\fR
.sp 9p
.RT
.PP
Refer to ISO 4903 (15\(hypole DTE/DCE interface connector and contact number
assignments) for mechanical arrangements.
.RT
.sp 1P
.LP
2.3
\fIFunctional characteristics of\fR
\fIinterchange circuits\fR
.sp 9p
.RT
.PP
Definitions of the interchange circuits concerned (see
Table\ 1/X.21) are given in Recommendation\ X.24.
.PP
In this Recommendation, signal conditions on interchange circuits T, C,
R, and I are designated by t, c, r, and i, respectively.
.PP
Signal conditions on circuit C (\fIControl\fR ) and I (\fIIndication\fR
) refer to continuous ON (significant level binary\ 0) and continuous OFF
(significant level binary\ 1) conditions.
.RT
.LP
.sp 1
.ce
\fBH.T. [T1.21]\fR
.ce
TABLE\ 1/X.21
.ps 9
.vs 11
.nr VS 11
.nr PS 9
.TS
center box;
cw(42p) | cw(60p) | cw(30p) sw(30p) | cw(42p) , ^ | ^ | c | c | ^ .
Interchange circuit Name Direction Remarks
to DCE from DCE
_
.T&
cw(42p) | lw(60p) | lw(30p) | lw(30p) | cw(42p) .
G T{
Signal ground or common return
T} See Note 1
.T&
cw(42p) | lw(60p) | cw(30p) | lw(30p) | cw(42p) .
G a DTE common return X
.T&
cw(42p) | lw(60p) | cw(30p) | lw(30p) | cw(42p) .
T Transmit X
.T&
cw(42p) | lw(60p) | cw(30p) | cw(30p) | cw(42p) .
R Receive X
.T&
cw(42p) | lw(60p) | cw(30p) | cw(30p) | cw(42p) .
C Control X
.T&
cw(42p) | lw(60p) | cw(30p) | cw(30p) | cw(42p) .
I Indication X
.T&
cw(42p) | lw(60p) | cw(30p) | cw(30p) | cw(42p) .
S Signal element timing X See Note 2
.T&
cw(42p) | lw(60p) | cw(30p) | cw(30p) | cw(42p) .
B Byte timing X See Note 3
.T&
cw(42p) | lw(60p) | cw(30p) | cw(30p) | cw(42p) .
X DTE signal element timing X See Note 4
.TE
.LP
\fINote 1\fR
\ \(em\ This conductor may be used to reduce environmental signal
interference at the interface. In the case of shielded interconnecting cable, the additional connection considerations are part of Recommendation\ X.24 and
ISO\ 4903.
.LP
\fINote 2\fR
\ \(em\ Timing for continuous isochronous data transmission will be
provided.
.LP
\fINote 3\fR
\ \(em\ May be provided as an optional additional facility (see \(sc\ 3.1.1
below).
.LP
\fINote 4\fR
\ \(em\ The use and the termination of this circuit by the DCE is a national matter.
.nr PS 9
.RT
.ad r
\fBTable 1/X.21 [T1.21], p.\fR
.sp 1P
.RT
.ad b
.RT
.LP
.sp 1
.sp 1P
.LP
2.4
\fIPhysical link control\fR \fIconditions\fR
.sp 9p
.RT
.PP
The DTE and DCE shall be prepared to send steady binary
conditions\ 0 and\ 1 on circuit R or T, together with associated
conditions on circuit\ C or I, for a period of at least 24\ bit intervals.
Detection of steady binary\ 0 or\ 1 on circuit\ R or\ T for 16 contiguous bit
intervals with the associated condition on circuit\ I or\ C may be interpreted
by the DTE or DCE as a steady state condition.
.PP
If the DTE (or DCE) recognizes that the device on the other side of
the interface is signalling recognition of the current state, then the
DTE (or DCE) may begin signalling the next valid state. If the DTE (or
DCE) is not
ready to begin signalling the next valid state, it is obliged to continue
signalling the current state until it is so ready.
.PP
\fINote\fR \ \(em\ As for state 12, \(sc 5.1 has precedence over this
\(sc\ 2.4.
.bp
.RT
.sp 1P
.LP
2.5
\fIQuiescent phase\fR
.sp 9p
.RT
.PP
During the quiescent phase, the DTE and the DCE signal their
ability to enter operational phases such as the call control phase or the
data transfer phase as defined for the appropriate service. The basic quiescent
signals of the DTE and the DCE can appear at the interface in various
combinations which result in different interface states as defined below and
shown in Figure\ A\(hy1/X.21.
.RT
.sp 2P
.LP
2.5.1
\fIDTE quiescent signals\fR
.sp 1P
.RT
.sp 1P
.LP
2.5.1.1
\fIDTE ready\fR
.sp 9p
.RT
.PP
The DTE indicates its readiness to enter operational phases,
according to the appropriate service, by signalling t\ =\ 1, c\ =\ OFF.
.RT
.sp 1P
.LP
2.5.1.2
\fIDTE uncontrolled not ready\fR
.sp 9p
.RT
.PP
The DTE indicates that it is unable to enter operational phases,
according to the appropriate service, generally because of abnormal operating
conditions, by signalling t\ =\ 0, c\ =\ OFF.
.PP
For leased circuit service point\(hyto\(hypoint when the DTE enters \fIDTE\fR
\fIuncontrolled not ready\fR , the remote interface may signal r\ =\ 0,
i\ =\ OFF.
Additional actions to be taken by the DCE are for further study.
.PP
For leased circuit\(hycentralized multipoint when a DTE enters \fIDTE\fR
\fIuncontrolled not ready\fR , no indication of this signal will be given
at the
other connected DTE/DCE interfaces.
.RT
.sp 1P
.LP
2.5.1.3
\fIDTE controlled not ready\fR
.sp 9p
.RT
.PP
\fIDTE controlled not ready\fR \|indicates that, although the DTE is
operational, it is temporarily unable to accept incoming calls for circuit
switched service.
.PP
This signal is indicated by t\ =\ 01 .\|.\|. (alternate bits are
binary\ 0 and binary\ 1), c\ =\ OFF. This signal shall persist for a minimum of
24\ bit intervals.
.PP
\fINote\fR \ \(em\ \fIDTE controlled not ready\fR \|is normally entered
from the
\fIready\fR state, as defined in \(sc\ 2.5.3.1 below. In some networks,
the DCE may not recognize the \fIDTE controlled not ready\fR signal if
the DTE does not first
signal \fIDTE ready\fR at the same time the DCE signals \fIDCE ready\fR .
.RT
.sp 2P
.LP
2.5.2
\fIDCE quiescent signals\fR
.sp 1P
.RT
.sp 1P
.LP
2.5.2.1
\fIDCE ready\fR
.sp 9p
.RT
.PP
The DCE indicates its readiness to enter operational phases,
according to the appropriate service, by signalling r\ =\ 1,
i\ =\ OFF.
.RT
.sp 1P
.LP
2.5.2.2
\fIDCE not ready\fR
.sp 9p
.RT
.PP
\fIDCE not ready\fR \|indicates that no service is available and will be
signalled whenever possible during network fault conditions and when test
loops are activated. This signal is indicated by r\ =\ 0, i\ =\ OFF.
.RT
.sp 1P
.LP
2.5.2.3
\fIDCE controlled not ready\fR
.sp 9p
.RT
.PP
\fIDCE controlled not ready\fR \|indicates that, although the DCE is
operational, it is temporarily unable to render service.
.PP
This signal is indicatd by r = 01\ .\|.\|.\ (alternate bits are binary
0 and binary\ 1), i\ =\ OFF. This signal shall persist for a minimum of
24\ bit
intervals.
.PP
\fINote\ 1\fR \ \(em\ \fIDCE controlled not ready\fR \|may be entered from
any state.
.PP
\fINote\ 2\fR \ \(em\ \fIDCE controlled not ready\fR \|may be provided
as an optional facility.
.bp
.RT
.sp 2P
.LP
2.5.3
\fIQuiescent states\fR \|(see Figure A\(hy1/X.21)
.sp 1P
.RT
.sp 1P
.LP
2.5.3.1
\fIReady (state 1)\fR
.sp 9p
.RT
.PP
\fIReady\fR \|is entered when the DTE and the DCE simultaneously signal
\fIDTE ready\fR \| and \fIDCE ready\fR , respectively.
.RT
.sp 1P
.LP
2.5.3.2
\fIState 14\fR
.sp 9p
.RT
.PP
State 14 is entered when the DTE and the DCE simultaneously signal \fIDTE
controlled not ready\fR \| and \fIDCE ready\fR , respectively.
.RT
.sp 1P
.LP
2.5.3.3
\fIState 18\fR
.sp 9p
.RT
.PP
State 18 is entered when the DTE and the DCE simultaneously signal \fIDTE
ready\fR \| and \fIDCE not ready\fR , respectively.
.RT
.sp 1P
.LP
2.5.3.4
\fIState 22\fR
.sp 9p
.RT
.PP
State 22 is entered when the DTE and the DCE simultaneously signal \fIDTE
uncontrolled not ready\fR \| and \fIDCE not ready\fR , respectively.
.RT
.sp 1P
.LP
2.5.3.5
\fIState 23\fR
.sp 9p
.RT
.PP
State 23 is entered when the DTE and the DCE simultaneously signal \fIDTE
controlled not ready\fR \| and \fIDCE not ready\fR , respectively.
.RT
.sp 1P
.LP
2.5.3.6
\fIState 24\fR
.sp 9p
.RT
.PP
State 24 is entered when the DTE and the DCE simultaneously signal \fIDTE
uncontrolled not ready\fR \| and \fIDCE ready\fR , respectively.
.RT
.sp 2P
.LP
2.6
\fIFailure detection\fR
.sp 1P
.RT
.sp 1P
.LP
2.6.1
\fIFault conditions of interchange circuits\fR
.FS
For the
association of the receiver circuit\(hyfailure detection to particular
interchange circuits in accordance with the type of failure detection,
see
Recommendation\ X.26, \(sc\ 11 and Recommendation\ X.27, \(sc\ 9.
.FE
.sp 9p
.RT
.PP
The DTE should interpret a fault condition on circuit R as r\ =\ 0, using
failure detection type\ 2, a fault condition on circuit\ I as i\ =\ OFF,
using failure detection type\ 1, and a fault condition on both circuits\
R and\ I as r\ =\ 0, i\ =\ OFF, \fIDCE not ready\fR . Alternatively, a
fault condition on one of these circuits, R\ or\ I, may be interpreted
by the DTE as \fIDCE not ready\fR ,
r\ =\ 0, i\ =\ OFF using failure detection type\ 3.
.PP
The DCE will interpret a fault condition on circuit T as t\ =\ 0, using
failure detection type\ 2, a fault condition on circuit C as c\ =\ OFF,
using
failure detection type\ 1, and a fault condition on both circuits\ T and\ C as
t\ =\ 0, c\ =\ OFF, \fIDTE uncontrolled not ready\fR . Alternatively, a
fault condition on one of these circuits, T\ or\ C, may be interpreted
by the DCE as \fIDTE\fR
\fIuncontrolled not ready\fR , t\ =\ 0, c\ =\ OFF using failure detection
type\ 3.
.RT
.sp 1P
.LP
2.6.2
\fIDCE fault conditions\fR
.sp 9p
.RT
.PP
If the DCE is unable to provide service (e.g., loss of alignment or loss
of incoming line signal) after a period longer than a fixed duration, it
will indicate \fIDCE not ready\fR by signalling r\ =\ 0, i\ =\ OFF (see
\(sc\ 2.5.2.2
above). The value of that duration is network dependent. Prior to this
\fIDCE\fR \fInot ready\fR signal, the DTE should be prepared to receive
garbled signals
or contiguous binary\ 1 on circuit\ R with i\ =\ ON.
.RT
.sp 1P
.LP
2.6.3
\fISignal element timing\fR \fIprovision\fR
.sp 9p
.RT
.PP
The signal element timing signal is delivered to the DTE on
circuit\ S whenever possible, even when the DCE loses alignment or the
incoming line signal. The signal element timing rate should in no case
deviate from the nominal value by more than \(+-\|1%.
.bp
.RT
.sp 2P
.LP
\fB3\fR \fBAlignment of call control characters and error checking\fR
.sp 1P
.RT
.PP
All characters for call control purposes are selected from
International Alphabet No.\ 5 according to Recommendation\ T.50.
.RT
.sp 1P
.LP
3.1
\fICharacter alignment\fR
.sp 9p
.RT
.PP
For the interchange of information between the DTE and the DCE for call
control purposes, it is necessary to establish correct alignment of
characters. Each sequence of call control characters to and from the DCE
shall be preceded by two or more contiguous 1/6 (SYN) characters.
.RT
.PP
3.1.1
Certain Administrations will require the DTE to align call
control characters transmitted from the DTE to either SYN characters delivered
to the DTE or to signals on the byte timing interchange circuit.
.PP
Administrations who require this alignment shall provide the byte timing
interchange circuit, but its use and termination by the DTE shall not be
mandatory.
.PP
3.1.2
Certain Administrations will permit call control characters to
be transmitted from the DTE independently of the SYN characters delivered to
the DTE.
.PP
3.1.3
Additionally, for an intermediate period (see Note),
Administrations will provide connection to the public data network of DTEs
operating as described in \(sc\ 3.1.2\ above.
.PP
\fINote\fR \ \(em\ The intermediate period would be determined by customer
demand and other relevant factors as interpreted by individual
Administrations.
.sp 1P
.LP
3.2
\fIError checking\fR
.sp 9p
.RT
.PP
Odd parity according to Recommendation X.4 applies for IA5
characters interchanged for call control purposes.
.RT
.sp 2P
.LP
\fB4\fR \fBElements of the\fR
\fBcall control phase for circuit switched\fR
\fBservice\fR
.sp 1P
.RT
.PP
The state diagram provided in Figure A\(hy2/X.21, shows the
relationship between the various \fIcall control\fR \| phase states as
defined below, together with the recognized transactions between these
states under normal
operating conditions. Illustrated examples of the time sequence relationships
between these states and associated time\(hyout operation are provided
in
Figures\ B\(hy1/X.21 and\ B\(hy2/X.21.
.PP
States which are indicated by an IA5 character on circuits T and R
shall be entered and exited on a character boundary. At this time, in some
networks, the transition from state\ 6 to state\ 11, or state\ 6 to state\
12 may not be on a character boundary.
.PP
Once character alignment has been established by the DCE in response to
an outgoing call request, or for presentation of an incoming call, the
alignment will be maintained until entering \fIconnection in progress\fR
, state\ 11 or \fIready for data\fR if state\ 11 is by\(hypassed. This
implies that all IA5
character sequences transmitted on circuit\ R, such as 2/11\ (\*Q+\*U),